Advanced Reliable Computer Systems Group

The Advanced Reliable Computer Systems (ARCoS) group, lead by Dr. Abusaleh Jabir, carries out leading research in the design, test, and verification of reliable computer systems. This includes architectural and systems level VLSI designs; security, power, and process variation aware designs; algebraic modeling of hardware; fault tolerance and testability. Application areas include reliable and efficient systems in submicron and nano technology, attack tolerant crypto hardware for improved security, mobile and wearable electronic devices, reliable remote sensors, etc.

In the areas of electronic design automation, the group’s research has gained world class success with the research and development of an automatic hardware synthesis tool called GfXpress™. This tool is designed for automatic hardware synthesis of algebraic polynomials over finite fields. The applications of this tool include high performance hardware designs for error detecting and correcting codes, testability, cryptography, high performance processor designs, digital signal processors, etc. Tests on industrial grade benchmarks demonstrated that, this tool is capable of up to two orders of magnitude improved results compared to leading industrial tools. The IP of this tool is patent pending, and now under going commercial exploitation.

The group has also enjoyed tremendous success in the areas of fault/error and attack tolerant hardware (Integrated Circuit) designs. The errors can result from any soft (transient) or hard (permanent) faults, either occurring naturally or injected maliciously, within the ICs. Unlike existing approaches, this group’s approaches are based on highly optimized hardware based advanced coding techniques. Tests showed that the proposed approaches are able to correct multiple errors simultaneously, with significantly lower overheads compared to existing approaches. These approaches can either be used on their own or in conjunction with other existing approaches, e.g. the triple modular redundancy (TMR), to provide with enhanced assurance for safety, security, and reliability. The IP of some of these approaches is patent pending, and now undergoing commercial exploitation.

The group’s research has contributed significantly in the areas of design for testability (DFT), with highly optimized testing techniques for bit parallel, serial, pipelined and systolic architectures. This also includes highly optimized built-in-self testability architectures to provide enhanced assurance for safety and security against side channel attacks in security critical applications, e.g. in crypto cores, etc.

The group has over 60 publications in these areas in premier journals and conferences such as the IEEE Transactions, ACM Transactions, the Proceedings of the IET, IEEE/ACM ICCAD, DATE, VLSI-SoC, ISQED, ECCTD, NORCHIP, etc. Funding sources include Commercialisation funding from Finance South East, QR funding for research and development, the EPSRC, etc. The group also has three filed patents, which are now being exploited for commercial ventures.