Dr Abusaleh Jabir

Reader

Abusaleh Jabir is a University Reader with the School of Technology, Oxford Brookes University. He completed a DPhil degree in Computing from the University of Oxford’s Computing Laboratory, where he was with the Hardware Compilation Group, a subdivision of the renowned Programming Research Group. Owing to the success of this group’s research in the design of the Handel-C hardware compiler, much of the groups resources later became a part of the Oxford University’s spin-off company, Celoxica Ltd, which marketed the Handel-C compiler. While completing his DPhil degree, he worked with Celoxica Ltd as a senior member of their research staff, prior to starting his career as a Senior Lecturer at Oxford Brookes University.

Dr. Jabir’s research record comprises more than 50 fully reviewed publications, best paper awards, book chapters, a patent, keynote paper, etc. He is also serving as member of program committee for IEEE conferences. He has an extensive experience in the research and development of Electronic Design Automation (EDA) tools for very large scale integrated (VLSI) circuits and systems. Dr Jabir was awarded the promising research fellowship with a one year research sabbatical in 2005 to 2006. Dr. Jabir’s recent research success has culminated into a prototype VLSI CAD tool, called GfXpress(TM), for automatic hardware synthesis of the polynomials over finite fields. The IP of this technique is patent pending, and is funded for commercial exploitation.


Research interests

  • Research interests include design, tests, and verification of secure VLSI systems with emphasis on their reliability and fault tolerance
  • High speed and reconfigurable architectures e.g. FPGAs, ultra low power design
  • System-on-Chip (SoC) and Network-on-Chip (NoC) based systems design with emphasis on their testability and reliability, hardware/ software cosynthesis
  • Cryptographic algorithms and their security aware, efficient, reliable, hardware realization, efficient hardware realization of algebraic structures

A part of this research has resulted in a new technique called ‘GfXpress™’, now patent pending, for automatic synthesis and optimisation of the polynomials over the finite fields. GfXpress™ is capable of synthesis and optimisation of the systems over these algebras nearly two orders of magnitude better (in terms of area, power, and delay) than the leading commercial tools. Some of the key crypto (e.g. ECC, AES, GCM, etc) and coding (e.g. Reed-Solomon, LDPC, BCH, etc.) techniques are described over these algebras and GfXpress™ is capable of optimising parts of these much better than any known technique. This technique, funded for commercial exploitation, is currently researched for its broader impact on optimising systems over other algebra.


Recent activity

  • US Patent No. 61/608,694, “Novel Cross Parity Based Error Tolerant Circuit Design”, filed on 9 March, 2012
  • Patent No. 1114831.9, “BCH Code Based Error Tolerant Electronic Circuit Design”,
    filed on 26 August, 2011
  • Invited guest speaker at Venturefest, 2011, Oxford, UK. The slides can be found here.

Teaching responsibilities

  • U08221: Object Oriented Software Development
  • U08921: Computer Systems
  • U08006: C & Unix (Co-lecturer and designer with Chris Cox)
  • P00999: MSc Project Dissertation–Module Leader and Coordinator

Awards and grants

Distinguished awards

Recipient of the IEE/IET best paper of the year award (Hartree Premium Award) for the paper “Minimization Algorithm for Three-LevelMixed AND-OR-EXOR/ AND-OR-EXNOR Representation of Boolean Functions”, which appeared in the IET Proceedings Part-E: Computers and Digital Techniques in 2002.

Commercialisation funding

CommercialISE funding of £50,000 from Finance South East, UK, for developing a Proof-of-Concept (PoC) tool. The PoC tool is for designing near optimal hardware from the polynomials over finite fields for commercial exploitation. The IP of this project is patent pending (Patent No: PCT/GB2007004206, “Near Optimal Polynomial Synthesis”, inventor Dr. Abusaleh Jabir).

Other funding

Fully Funded PhD Studentship for 3 years in Fault Tolerant Efficient Crypto hardware synthesis. One year post doctoral fellowship in Fault tolerant hardware architectures.


Publications

  • M. Poolakkaparambil, J. Mathew, A. Jabir, and D. Pradhan. A Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes over GF(2m). IEEE Trans. VLSI (accepted), July 2014.
  • J. Mathew, A. Jabir, R. Shafik, and D. Pradhan. Power efficient fault tolerant finite field multiplier. In D. Pradhan et. al., editor, Energy Efficient Fault Tolerant Systems. Springer, 2013. (In press).
  • J. Mathew, S. Mohanty, S. Banerjee, D. Pradhan, and A. Jabir. Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. Elsevier Journal of Comp. and Elect. Eng., 2013.
    DOI: http://dx.doi.org/10.1016/j.compeleceng.2013.01.001.
  • C. T. Veedon, A. M. Jabir, M. Poolakaparambil, and J. Mathew. On the design of Trojan tolerant finite field multipliers. In IEEE Int. Multi Conf. Auto. Comp. Control. & Comp. Sensing (iMac4s'2013), Kerala, India, March 2013.
  • H. Rahaman, J. Mathew, A. Jabir, and D. Pradhan. VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m) Using Dual Bases. Lecture Notes in Computer Science, Springer-Verlag, pages 258-269, 2012.
  • C.T. Veedon, M. Poolakkaprambil, and A. Jabir. Design and Analysis of Trojan Tolerant Finite Field Architecture. In Proc. Int. Workshop. Applicat. Signal Processing (I-WASP) (accepted), Kerala, India, August 2012.
  • M. Poolakkaparambil, J. Mathew, and A. Jabir. Multiple Bit Error Tolerant Galois Field Architectures Over GF(2m). International Journal of Electronics (Open Access), ISSN 2079-9292 (accepted), 2012.
  • M. Poolakkaparambil, J. Mathew, A. Jabir, and S. Mohanty. Concurrent Error Detection Over Binary Galois Fields in CNTFET and QCA technologies. In Proc. IEEE Int. Symp. on VLSI (ISVLSI'2012) (accepted), Texas, USA, August 2012.
  • H. Rahaman, J. Mathew, A. Jabir, and D. Pradhan. VLSI Architecture for Bit-Parallel Systolic Multipliers for Special Class of GF(2m) Using Dual Bases. In Proc. VLSI Des. and Test. Symp (VDAT'2012) (accepted), Shibpur, India, July 2012.
  • M. Poolakkaparambil, J. Mathew, and A. Jabir. Fault Resilient Galois Field Multiplier Design in Emerging Technologies. In Proc. Int. Conf. on Eco-friendly Comp. and Comm. Systems (ICECCS'2012, also to appear in Springer Lecture Notes in Computer Science (LNCS)) (accepted), Kerala, India, August 2012.
  • M. Poolakkaparambil, J. Mathew, A. Jabir, and S. Mohanty. Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction. In Proc. IEEE/ACM Int. Symp. Quality Electronic Design (ISQED'2012) (accepted), Santa Clara, USA, March 2012.
  • M. Poolakkaparambil, A. Jabir, J. Mathew, and D. Pradhan. Cross parity based error tolerant electronic circuit design. In US Patent No. 61/608,694. Filed on 9 March, 2012.
  • M. Poolakkaparambil, J. Mathew, and A. Jabir. A Dynamically Error Correctable Bit Parallel Montgomery Multiplier Over Binary Extension Fields. In Proc. IEEE European Conf. Circuit Theory and Des. (ECCTD'2011) (accepted), Linköping, Sweden, August 2011.
  • M. Poolakkaparambil, A. Jabir, J. Mathew, and D. Pradhan. BCH Code Based Dynamically Error Correctable Electronic Circuit Design. In Patent No. 1114831.9. Filed on 26 August, 2011.
  • M. Poolakkaparambil, J. Mathew, A. Jabir, and D. Pradhan. BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits. In Proc. IEEE/ACM Int. Symp. Quality Electronic Design (ISQED'2011) (accepted), Santa Clara, USA, March 2011.
  • J. Mathew, M. Poolakkaparambil, A. Jabir, and D. Pradhan. Multiple Bit Error Detection and Correction in GF Arithmetic Circuits. In Proc. IEEE Int. Symp. Elect. Sys. Design (ISED'2010) (accepted), Bhubaneswar, India, December 2010.
  • J. Mathew, A. Jabir, A. Singh, H. Rahaman, and D. Pradhan. A Galois Field Based Logic Synthesis Approach with Testability. IET Proc. Part-E: Comp. Digital Tech, 4(4):263-273, 2010.
  • J. Mathew, S. Banerjee, D. Pradhan, and A. Jabir. On the Synthesis of Attack Tolerant Cryptographic Hardware. In Proc. 18th IEEE/IFIP Int. Conf. on VLSI and System-on-Chip (VLSI-SoC) (accepted), Madrid, Spain, September 2010.
  • H. Rahaman, J. Mathew, A. Jabir, and D. Pradhan. VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m) using Dual Bases. In Proc. CSI Symp. on Comp. Architecture. and Dig. Systems (CADS'10) (accepted), September 2010.
  • J. Mathew, H. Rahaman, A. Jabir, S.P. Mohanty, and D. Pradhan. On the Design of Different Concurrent EDC Schemes for S-Box and GF(p). In Proc. IEEE/ACM Int. Symp. on Quality Electronics Design (ISQED'10), San Jose, California, USA, March 2010.
  • H. Rahaman, J. Mathew, A. Jabir, and D. Pradhan. Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability. Proc. IET Part-E: Comp. and Digital Tech., 4(5):428-437, February 2010.
  • J. Mathew, A. Jabir, H. Rahaman, and D. Pradhan. On the Synthesis of Bit Parallel Galois Field Multipliers with On-line SEC and DED. Int. Journal of Electronics, 96(11):1161-1173, November 2009.M
  • J. Mathew, A. Jabir, H. Rahaman, and D. Pradhan. Single Error Correctable Bit Parallel Multipliers over GF(2m). IET Proc. Part-E: Comp. Digital Tech, 3(3):281-288, 2009.
  • M. Ciesielski, A. Jabir, and D. Pradhan. Practical design verification. In I. Haris, editor, Decision Diagrams for Verification. Cambridge University Press, 2009.
  • H. Rahaman, J. Mathew, A. Jabir, and D. Pradhan. C-Testable S-Box Implementation for Secure Advanced Encryption Standard. In Proc. IEEE On-Line Testing Symposium (IOLTS'08), Sesimbra-Lisbon, Portugal, June 2009.
  • H. Rahaman, J. Mathew, A. Jabir, and D. Pradhan. Derivation of Reduced Test Vectors for Bit Parallel Multipliers over GF(2m). IEEE Trans. Comp., 59(9):1289-1294, September 2008.
  • A. Jabir, D. Pradhan, and J. Mathew. GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. IEEE Trans. CAD, 27(4):690-711, April 2008.
  • J. Mathew, A. Jabir, and D. Pradhan. Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. In IEEE On-Line Testing Symposium (IOLTS'08), Rhodes, Greece, July 2008.
  • J. Mathew, A. Jabir, and D. Pradhan. Fault Tolerant Bit Parallel Finite Field Multipliers Using LDPC Codes. In Int. Symp. Circuits and System. (ISCAS'08), Seattle, USA, May 2008.
  • J. Mathew, H. Rahaman, A. Jabir, A. Singh, and D. Pradhan. A Galois Field Based Logic Synthesis Approach with Testability. In Proc. IEEE/ACM Int. Conf. on VLSI Design (VLSI'08), pages 629-634, Hyderabad, India, January 2008.
  • J. Mathew, A. Jabir, H. Rahaman, and D. Pradhan. Single Error Correcting Multipliers Over GF(2m). In Proc. IEEE/ACM Int. Conf. on VLSI Design (VLSI'08), pages 33-38, Hyderabad, India, January 2008.
  • H. Rahaman, J. Mathew, A. Jabir, and D. Pradhan. C-Testable Bit-Parallel Multipliers Over GF(2m). ACM Trans. Des. Automat. Elect. Systems (TOADES), 13(5), January 2008.
  • J. Mathew, H. Rahaman, A. Jabir, and D. Pradhan. Area Efficient Pseudo-Parallel Galois Field Multipliers. In Proc. IEEE NORCHIP'07, Aalborg, Denmark, October 2007.
  • A. Jabir, D. Pradhan, A. Singh, and T.L. Rajaprabhu. A Technique for Representing Multiple-Output Binary Functions with Applications to Verification and Simulation. IEEE Trans. Comp., 56(8):1133-1145, August 2007.
  • A. Jabir and D. Pradhan. A Graph-Based Unified Technique for Computing and Representing Coefficients Over Finite Fields. IEEE Trans. Comp., 56(8):1119-1132, August 2007.
  • A. Jabir. An Efficient Approach to Synthesis and Optimization of GF(2m) Polynomials in Hardware. In UK/International patent No. PCT/GB2007/004206 pending. Filed on 3 November, 2006.
  • A. Jabir, D. Pradhan, and J. Mathew. An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m). In Int. Conf. Comp. Aided. Design (ICCAD), pages 151-157, Silicon Valley, USA, November 2006.
  • J. Mathew, A. Jabir, A. Singh, and D. Pradhan. Galois Decomposition of Boolean Functions: An Efficient Synthesis Approach with Testability. In Proc. IEEE International Design and Test Workshop (IDT'2006), Dubai, UAE, November 2006.
  • H. Rahaman, J. Mathew, A. Jabir, and D. Pradhan. Universal Test Set for Detecting Faults in Bit Parallel Multipliers in GF(2m). In Proc. IEEE High Level Des. Val. Test Workshop (HLDVT'06), San Jose, California, November 2006.
  • A. Jabir. Core Based Systems Design: The Present and the Future-A distinguished keynote paper. In Proc. Int. Conf. Comp. and Inf. Tech. (ICCIT'05), pages 1256-1262, December 2005.
  • M.S. Hasan, B.P. Amavasai, J.R. Travis, Hongnian Yu, and A. Jabir. An Exhaustive Search Approach to the Boolean Satisfiability Problem for Distributed Computing Environment. In Proc. Int. Conf. Comp. and Inf. Tech. (ICCIT'05), pages 449-452, December 2005.
  • A. Jabir and D. Pradhan. An Efficient Graph Based Representation of Circuits and Calculation of Their Coefficients in Finite Field. In Proc. Int. Workshop on Logic and Synth. (IWLS'05), pages 218-225, California, USA, June 2005.
  • T.L. Rajaprabhu, A. Singh, A. Jabir, and D. Pradhan. GASIM: A Fast Galois Field Based Simulator for Functional Model. In Proc. IEEE Int. High Level Des. Val. and Test Workshop (HLDVT'05), pages 135-142, California, USA, December 2005.
  • A. Jabir, T.L. Rajaprabhu, A. Singh, and D. Pradhan. Galois Switching Theory: A Uniform Framework For Multi-Level Verification. In Int. Workshop. Logic and Synth (IWLS'05), pages 234-240, California, USA, June 2005.
  • M.S. Hasan and A. Jabir. An Artificial Intelligence Method for the Boolean Satisfiability Problem. In Proc. Int. Conf. Comp. Inf. Tech. (ICCIT'04), December 2004.
  • T. Rajaprabhu, A. Singh A. Jabir, and D. Pradhan. MODD For CF: A Compact Representation for Multiple-Output Functions. In Proc. IEEE Int. High Level Des. Val. Test Workshop (HLDVT'04), California, USA, November 2004.
  • M.S. Hasan and A. Jabir. A New Genetic Algorithmic Solution to the Bookean Satisfiability Problem. In Proc. Int. Conf. Comp. Sci. and App. (ICCSA'04), California, USA, 2004.
  • A. Jabir, T. Rajaprabhus, D. Pradhan, and A. Singh. Galois Switching Theory: A Unified Framework for Multi-Level Verification,. In Proc. IEE-ACM SIGDA SoC Des. Test. and Tech. Seminar, Leicester, UK, September 2004.
  • A. Jabir and D. Pradhan. MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. In Des. Automat. Test. in Europe (DATE'04), pages 1388-1389, Paris, France, February 2004.
  • A. Jabir and D. Pradhan. Designing Multiple-Valued Networks in a Finite Field. In 6th Int. Conf. Comp. and Inf. Tech. (ICCIT'03), December 2003.
  • A. Jabir and D. Pradhan. A Theory of Finite Field Decision Diagrams. Technical report, Department of Computer Science, University of Bristol, November 2003.
  • A. Jabir and J. Saul. Minimization Algorithm for Three-Level Mixed AND-OR-EXOR/AND-OR-EXNOR Representation of Boolean Functions. IEE Proc. E, 149(3):82-96, May 2002. [Winner of the IEE best paper of the year award (IEE Hartree Premium Award) in Computing and Digital Techniques, 2003/2004].
  • A. Jabir. Logic Minimization Algorithms for Three-Level AND-OR-EXOR Representations. DPhil Thesis, St. Cross College, University of Oxford, Trinity Term, 2001.
  • A. Jabir and J. Saul. Heuristic AND-OR-EXOR three-level minimisation algorithm for multiple-output incompletely-specified Boolean functions. IEE Proc. E, 147(6):451-461, November 2000.
  • M. Rafiqul, A. Jabir, and M. Mottalib. Design for Testing of Plas with Input Decoder Augmentation. Dhaka Univ. J. Sci., 47(1):35-42, 1999.
  • M. Rafiqul, A. Jabir, and M. Mottalib. Design for Testing of PLAs with Input Decoder Augmentation. In Proc. Int. Conf. Compt. Inf. Tech. (ICCIT'99), pages 279-283, Dhaka, Bangladesh, December 1999.
  • A. Jabir and J. Saul. A Heuristic Decomposition Algorithm for AND-OR-EXOR Three-Level Minimization of Boolean Functions. In Proc. 4th Int. Workshop Applicat. Reed-Müller Expansion in Circuit Design, pages 55-72, Victoria, Canada, August 1999.
  • M. Rafiqul, A. Jabir, and M. Mottalib. An Improved Algorithm for Parallel Testing of PLAs. Dhaka Univ. J. Sci., 46(2):185-227, 1998.
  • M.A. Mottalib and A.M. Jabir. A Simultaneously Testable PLA with High Fault Coverage and Reduced Test-Set. IETE J. Res., 1(1):41-48, Jan-Feb 1997.
  • A. Jabir and M. Mottalib. A Simultaneously Testable PLA with Improved Product Line Partitioning Conditions. Dhaka. Univ. J. Sci., 45(2):179-190, July 1997.
  • M. Rafiqul, A. Jabir, and M. Mottalib. An Improved Design for Simultaneously Testable PLAs with Reduced Test Set. In Proc. Nat. Conf. Comp. Inf. Tech. (NCCIT'97), page 314, Dhaka, Bangladesh, 1997.
  • M. Rafiqul, A. Jabir, and M. Mottalib. Improved Design of Easily-Testable PLA with Input Decoder Augmentation. Bangladesh Sci. Ind. Res. (BCSIR) J., 1996.
  • A. Jabir and M. Mottalib. An Improved BIST PLA with Product-Line Grouping. J. Bangladesh Elect. Soc., 4(1):41-45, December 1994.
  • A. Jabir and M. Mottalib. A Two Pass Cross-Assembler with Improved Datastructure. Bangladesh Sci. Ind. Res. (BCSIR) J., 1994.